Attendees enjoy expanded program and engaging, sold-out exhibit floor

LOUISVILLE, Colo., March 05, 2019 (GLOBE NEWSWIRE) -- The 2019 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 31st annual event last week with attendees filling rooms to learn more about machine learning, Portable Stimulus, multi-platform verification, what "digital twin" means and more.  The DVCon Expo was sold out this year with 32 exhibitors filling the ballroom.   

Overall attendance, including exhibit-only and technical conference attendees, was 873.  Attendance was further enhanced by 240 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,113 participants. 

“We are very pleased with the increased turnout and the positive reception of our program at DVCon U.S. 2019,” stated Aparna Dey, DVCon U.S. General Chair.  “Our evolving program continues to be a strong resource for the latest information, tips and tricks for the practicing design and verification engineer.  We are very proud that our technical program, tutorials, short workshops and panels not only covered key verification topics, but also included a number of new topics that attracted standing-room-only attendance.  Our exhibition was a major draw for both attendees and exhibitors and was a gathering place each afternoon for the DV engineers and their peers to discuss the latest in technology and design.”

In honor of his significant contributions to Accellera and DVCon, the Best Paper Award has been posthumously named the Stuart Sutherland Best Paper Award.  Stu was recognized around the world as a Verilog and SystemVerilog expert and had a tremendous impact on the industry.  He was a past General Chair of DVCon U.S. as well as a member of the Technical Program Committee (TPC) for many years.

The award for the first Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to Cliff Cummings, Sunburst Design, Inc., and John Rose and Adam Sherer, Cadence Design Systems for their presentation, “Yikes! Why Is My SystemVerilog Still So Slooooow?”  Second place was awarded to Horace Chan and Byron Watt, Microchip Technology, Inc. for their presentation, “How to Test the Whole Firmware/Software when the RTL Can’t Fit the Emulator,” and third place was awarded to Ang Li, Hao Chen, Jason Yu, EeLoon Teoh, and Iswerya Prem Anand, Intel Corp. for their paper, “­­­­­­A Coverage-Driven Formal Methodology for Verification Sign-off.”

Top honors for Best Poster went to Srikanth Reddy Rolla, Vijayakrishnan Rousseau, Suresh Balasubramanian, Mohamed Saheel Nandikotkur Hussainsaheb, Intel Corp. for their poster, “Emulation Testbench Optimizations for Better Hardware Software Co-Validation.”  Second place was awarded to Mohamed Saheel Nandikotkur Hussainsaheb, Suresh Balasubramanian and Vijayakrishnan Rousseau, Intel Corp. for their poster, “Novel Approach to ASIC Prototyping.”  Third place was awarded to Luis Li, Pablo Salazar and Andres Cordero, Hewlett Packard Enterprise for their poster, “Verification Reuse for a Non-Transaction Based Design Across Multiple Platforms.”

“Because of their close relationship over the years and their combined efforts in the development and adoption of industry standards, it was particularly poignant that Cliff Cummings was part of the team that received the first Stuart Sutherland Best Paper Award,” stated Tom Fitzpatrick, DVCon U.S. Technical Program Committee Chair.  “In addition to Cliff, I’d like to congratulate all of our paper and poster winners this year.  They each did an outstanding job of providing material that our attendees find extremely valuable and useful in their day-to-day jobs.  I’m also very proud of the TPC and the overall technical program we were able to provide to attendees this year.  There is a huge demand for increasing automation when it comes to the task of verification.  To address the interest in this topic we were able to provide two sessions on verification strategies, two on Portable Stimulus, and one on big data and verification.  With growing interest in this and other topics, we are looking at ways to expand the technical program in 2020. Stay tuned.”

Highlights of the Week: 

• For his many years of dedication to the advancement of standards, Fitzpatrick was honored during the Accellera-sponsored luncheon on Monday as the recipient of the eighth annual Accellera Technical Excellence Award.  In addition to his TPC chair position, he is Strategic Verification Architect at Mentor, a Siemens Business and a noted verification evangelist.

• On Tuesday Fram Akiki, vice president, Electronics & Semiconductor Industry for Siemens PLM Software, provided the keynote focusing on digital transformation.  Broadening the scope beyond Electronic Design Automation, he highlighted IC verification as an important foundation for extending the digital twin into important applications such as autonomous driving and intelligent, connected devices.  The standing-room-only crowd enjoyed the lively and thought-provoking presentation.

• There were two panels on Wednesday.  The first panel, “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming Tsunami of Innovation?” explored the hot topic of the RISC-V instruction set architecture, its features and benefits as well as the challenges for processor IP and SoC development and verification.  The second panel, “Deep Learning –– Reshaping the Verification Landscape or Business as Usual?” had a packed ballroom of attendees learning about the next steps for AI and machine learning and how they will reshape the semiconductor industry. 

• Short workshops, which were added to the program last year to give attendees the opportunity to hear from a wider set of vendor companies at DVCon, have been so well-received by attendees that more were added to the program this year.  Nine short workshops were offered, many at capacity, and some of which offered participants a hands-on experience.

The DVCon Steering Committee values all feedback regarding the conference.  Attendees have been given a survey and are asked to provide input on how to make DVCon U.S. 2020 even better.

Save the date:  DVCon U.S. 2020 will be held March 2-5 at the DoubleTree Hotel in San Jose, California.  

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

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